Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components such as dies that are connected by various interconnect components. The dies may include memory, logic or other integrated circuit (IC) device.
ICs may be implemented to perform specified functions. Example ICs include mask-programmable ICs, such as general purpose ICs, application specific integrated circuits (ASICs), and the like, and field programmable ICs, such as field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and the like.
ICs have become more “dense” over time, i.e., more logic features have been implemented in an IC. More recently, Stacked-Silicon Interconnect Technology (“SSIT”) allows for more than one semiconductor die to be placed in a single package. SS IT ICs may be used to address increased demand for having various ICs within a single package. Conventionally, SSIT products are implemented using an interposer that includes an interposer substrate layer with through-silicon-vias (TSVs) and additional metallization layers built on top of the interposer substrate layer. The interposer provides connectivity between the IC dies and the package substrate.
Chip-to-chip interfaces (also called interconnects) provide a bridge between host devices, such as between ICs, system-on-chip (SoCs), FPGAs, ASICs, central processing units (CPUs), graphic processing units (GPUs), etc.
As the data rates which can be processed by systems increases, providing interfaces that can keep up with the processing speed of the chip becomes increasingly difficult. Power-efficient, robust, and low-cost chip-to-chip interfaces are desirable to meet the needs of high-performance systems.
High speed chip-to-chip interfaces sometime involve tradeoffs between pin count, input/output (I/O) die area, power, etc. Some examples of chip-to-chip interfaces include low voltage complementary metal oxide semiconductor (LVCMOS) I/O, low voltage differential signaling (LVDS) I/O, high speed serializer/deserializer (SERDES) I/O.
High bandwidth memory (HBM) is a high-performance random access memory (RAM) interface for 3D-stacked dynamic RAM (DRAM) and has been adopted by the Joint Electron Device Engineering Council (JEDEC) standards body. The HBM standard defines a new type of physical interface for communication between an HBM DRAM device and a host device such as an ASIC, CPU, GPU, or FPGA. The HBM physical interface can improve tradeoff point as far as I/O die area and power as compared to certain other interfaces. HBM can achieve high bandwidth using less power in a small form factor.
For some systems, a high speed interface is desirable to efficiently integrate other host devices on a single interposer. Thus, techniques for a high bandwidth chip-to-chip interface would be useful.